A Python/Qt demonstration app and core IP for the PolarFire DISCOVERY board, reverse engineered from the Verilog and screenshots of the Windows app
  • SystemVerilog 57.9%
  • Python 38.9%
  • Makefile 3.2%
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2026-10-07 14:19:31 +11:00
AN5165 Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
Board Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
CoreIP Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
Lib Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
tools Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
.gitignore Edited files for the rearranged directory structure 2026-10-06 21:24:38 +11:00
Makefile Reworked documentation substantially to follow a new writing style guide 2026-10-07 14:19:31 +11:00
pytest.ini Rearranged directory structure. Next commit will change file contents to suit 2026-10-06 21:24:11 +11:00
requirements.txt Fully reverse engineered the CoreFFT hardware and documented all as CoreDSP.md 2026-10-04 19:11:44 +11:00