Altera Cyclone IV FPGA board (EP4CE6E22C8N)

These cheap boards (another and another) are available from a number of different AliExpress sellers.

The one I used looks like this .

Most of the sellers also sell clone or replacement USB Blaster dongles. Some replacements do not work - you must have a clone or better - see below.

The board provides:

• I/O flexibility to handle 3.3V, 2.5V, 1.8V, 1.2V.
• two banks of 24 I/O pins
• two sets of jumpers to set the operating voltage of the two I/O banks
• a CH340 USB serial chip connected to FPGA pins
• the power supply regulators (from USB)
• five push buttons
• four LEDs
• a 50MHz crystal clock, and a separate 27MHz clock
• an EPCS4N 1MBit configuration flash chip (which requires using ActiveSerial, see below)
• an Winbond W25Q64JV 8MByte serial flash.
• the EP4CE6E22C8N FPGA, see the handbook

Prerequisites to build this project

Quartus Prime Lite Edition

This software is free for use, but you must obtain and annually refresh a license key. I installed version 22.1std, but a newer version is now available.

A Linux computer

I used Debian, but any recent Linux should work. You need 20GB free, mostly to install Quartus (usually into /opt/intelFPGA_lite).

A USB Blaster

There are cheap (under $3) USB Blasters which use a CH552 microprocessor. These do not work with Linux.

You need one with a CPLD to generate the correct waveforms. My one uses an FT245 and EPM3064AE, with a 74LVC125 as level shifter.

In the bad old days you needed to perform magic in "udev" for these devices to be recognised and permitted. If you have this problem, here is some advice.

I have the following rule in /etc/udev/rules.d/90-usb-blaster.rules:

    SUBSYSTEM=="usb", ATTR{idVendor}=="09fb", ATTR{idProduct}=="6001", MODE="0666", RUN+="/bin/chmod 0666 %c"

After adding this file, use the command sudo udevadm control --reload to load it, then reconnect the USB Blaster.

If you want to use jtagd interactively, ensure it can find the list of devices. I used this:

sudo cp /opt/intelFPGA_lite/22.1std/quartus/linux64/pgm_parts.txt /etc/jtagd/jtagd.pgm_parts 

At this point, jtagconfig should list your USB Blaster.

If your FPGA board was also connected and powered over USB, it should also be detected.

Projects layout

At this top level, there is a lib directory containing SystemVerilog modules, and a pin_configuration.tcl file which describes this board by assigning names to pins and sets the voltages for the pin banks.

There may be multiple project directories. Each directory contains a Quartus Project File QPF and a QSF file, as well as one SV file which describes its top level, and uses modules from the lib directory. Each project also contains a Synopsys Design Constraints (SDC) file, which provides advice to the Timing Analyser.

For example, in the button_flasher directory the main source file is C4Blinkie.sv. It expects a 50MHz clock, four buttons and five LEDs. It displays a pattern on the five LEDs:

• LED[4] flashes twice per second
• LED[3] is off
• LED[2] is on when you press BUTTON[0]
• LED[1] is off
• LED[0] flashes out of phase with LED[4] wile you hold the button

The 2Hz clock is generated using the clock_divider module from lib.

Compiling these projects

You should change to one of these sub-directories and open the QPF file in Quartus.

Select Processing->Start Compilation to compile the code.

All projects produce many temporary files into the project directory (and sub-directories), and the main output files into the top-level build directory. The SOF file contains the compiled bitstream.

You should remove this build directory when changing projects, and may clean up the temporary directories at any time.

Running

Using Tools->Programmer, check that the ByteBlaster is found, then you should "Auto Detect" the hardware. This will show the FPGA, but not the Configuration Flash, because Active Serial flash can not be automatically detected. The FPGA family is detected and about a dozen family members are listed. You will need to select EP4CE6 from the bottomn of the displayed list.

The detected JTAG chain configuration is saved in a Chain Definition File, CDF.

Converting the bitstream to program Active Serial configuration flash

Running the SOF file loads it into the FPGA's static RAM, which is lost after power on. This board uses Active Serial flash, which requires that you translate the SOF file to a JIC file. This uses a method similar to the one documented here.

The steps are:

1. Use File->Convert Programming File to open the conversion dialog.
2. Change the Programming file type to “JTAG Indirect Configuration File”
3. Select the “EPCS4N” configuration device and “Active Serial” mode
4. Provide an output file name, such as C4Blinkie_EPCS4N.jic
5. In the “Input files to convert section:
   • SOF Data” and select “Add File..." to add output_files/C4Blinkie.sof
   • Click on "Flash Loader" in the list and select "Add Device..."
   • Select EPCS4N from the Cyclone IV parts list
6. Click "Generate" and check that the JIC file was created
7. Save this configuration data as a COF file

Storing the bitstream Active Serial configuration flash

1. Connect the USB Blaster and power the board
2. Select Tools->Programmer
3. Select "Add File" and choose the JIC file
4. Check the boxes under “Program/Configure” and “Verify” next to this file in the list
5. The FPGA must also be programmed, but replace the contents of the File column with “Factory default enhanced SFL image”
6. Select "Start". This may take some time.
7. Remove power from the board, change configuration to make it boot from Active Serial, and power it again.

More information on this procedure may be found in AN370 frm Altera

Documentation

A reverse-engineered schematic seems to be mostly correct.

There is a VHDL project for this board.